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| device operating temperature range package semiconductor technical data basic octal serial switch (spi input/output) ordering information MC33291Ldw t c = 40 to 125 c sop24l order this document by MC33291L/d pin connections dw suffix plastic package case 751e sop (16+4+4)l 24 1 sop24l function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 output 7 output 6 sclk si ground ground ground ground so csb output 5 output 4 output 3 output 2 sfpd v dd ground ground ground ground v pwr reset output 1 output 0 1 motorola analog ic device data the MC33291L is an eight output low side power switch with 8bit serial input control. the MC33291L is a versatile circuit designed for automotive applications, but is well suited for other environments. the MC33291L incorporates smartmos ? technology, with cmos logic, bipolar/mos analog circuitry, and dmos power mosfets. the MC33291L interfaces directly with a microcontroller to control various inductive or incandescent loads. the circuit's innovative monitoring and protection features are: very low standby current, spi cascadable fault reporting, internal 53 v clamp on each output, output specific diagnostics, and independent shutdown of outputs. the device is parametrically specified over an ambient temperature range of 40 c t a 125 c and 9.0 v v pwr 16 v supply. the economical so24 wide body surface mount plastic packages make the MC33291L a very cost effective solution for many applications. ? designed to operate over wide supply voltages of 5.5 to 26.5 v ? interfaces directly with microprocessor using 8bit spi i/o protocol to 3.0 mhz ? 1.0 a peak current outputs with maximum r ds(on) of 1.6 w at t j = 150 c ? outputs current limited to 1.0 to 3.0 a for switching incandescent loads ? output voltages clamped to 53 v during inductive switching ? maximum sleep current (i pwr ) of 25 m a with reset low ? maximum of 4.0 ma i dd during operation ? maximum of 2.0 ma i pwr during operation with all outputs on ? open load detection (outputs off) ? overvoltage detection and shutdown ? outputs have independent over temperature detection and shutdown ? output mode programmable for sustained current limit or shutdown ? independent output short circuit detect and latchoff for every write cycle ? designed for 40 to 125 c ambient temperature operation %:4a? 4?>ca?<<6a f:c9 db . 32c +$# + + ( +' . (/* . %'+ +6a:2< +9:7c *68:bc6ab 2>5 $2c496b %'+ !>@dc $?8:4 -@5a2:> %'+ 'dc@dc +f:c496b 2>5 +6>b6 :a4d:cb +! *6b6c + ( 'dc@dc 'dc@dc 'dc@dc 'dc@dc 'dc@dc 'dc@dc 'dc@dc 'dc@dc a?d>5 this device contains 1266 active transistors. simplified application schematic ? motorola, inc. 2001 rev 0 MC33291L 2 motorola analog ic device data ! $:=:c 'dc@dc * + '@6> $?25 6c64c +9?ac :a4d:c 6c64c 'e6a ,6=@6a2cda6 6c64c +' +! +$# + *6b6c + ( . 2c6 ?>ca?< . 'dc@dcb ic?i a?d>5b figure 1. internal block diagram 'e6ae? MC33291L 3 motorola analog ic device data maximum ratings (all voltages are with respect to ground, unless otherwise noted.) rating symbol value unit power supply voltage steadystate v pwr(sus) 1.5 to 26.5 v transient conditions (note 1) v pwr(pk) 13 to 60 v logic supply voltage (note 2) v dd 0.3 to 7.0 v input pin voltage (note 3) v in 0.3 to 7.0 v output clamp voltage (note 4) v out(off) v (5.0 ma i out 0.5 a) 45 to 65 output self limit current i out(lim) 1.0 to 3.0 a continuous per output current (note 5) i out(cont) 500 ma esd voltage (note 6) human body model (note 7) v esd1 2000 v machine model (note 8) v esd2 200 v output clamp energy (note 9) e clamp 50 mj recommended frequency of spi operation f spi 3.0 mhz storage temperature t stg 55 to 150 c operating case temperature t c 40 to 125 c operating junction temperature t j 40 to 150 c power dissipation (t a =25 c) (note 10) p d 2.0 w lead soldering temperature (note 13) t solder 260 c thermal resistance (junctiontoambient) r q ja c/w so24 package all outputs on (note 11) 45 single output on (note 12) 60 notes: 1. transient capability with external 100 w resistor connected in series with v pwr pin and supply. 2. exceeding these limits may cause a malfunction or permanent damage to the device. 3. exceeding these limits on sclk, si, csb, sfpd, or reset pins may cause permanent damage to the device. 4. with output off. 5. continuous output rating so long as maximum junction temperature is not exceeded. operation at 125 c ambient temperature will require maximum output current computation using package r q ja . 6. esd data available upon request. 7. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 w ). 8. esd2 testing is performed in accordance with the machine model (c zap = 100 pf, r zap = 0 w ). 9. maximum ouput clamp energy capability at 150 c junction temperature using single nonrepetitive pulse method. 10. maximum power dissipation at indicated junction temperature with no heat sink used. 11. thermal resistance from junctiontoambient with all outputs on and dissipating equal power. 12. thermal resistance from junctiontoambient with a single output on. 13. lead soldering temperature limit is for 10 seconds maximum duration; contact motorola sales office for device immersion soldering time/temperature limits. MC33291L 4 motorola analog ic device data static electrical characteristics (characteristics noted under conditions of 4.5 v v dd 5.5 v, 9.0 v v pwr 16 v, 40 c t c 125 c, unless otherwise noted. typical values, where applicable, reflect the parameter's approximate average value with v bat = 13 v, t a = 25 c.) characteristic symbol min typ max unit power input supply voltage range v quasifunctional (note 1) v pwr(qf) 5.5 9.0 fully operational v pwr(fo) 9.0 26.5 supply current (all outputs on, i out = 0.5 a) i pwr(on) 1.0 2.0 ma sleep state supply current at reset 0.2 v dd and/or v dd < 0.5 v i pwr(ss) 1.0 25 m a sleep state output leakage current (per output, reset = 0) i out(ss) 1.0 25 m a overvoltage shutdown v ov 28 32 36 v overvoltage shutdown hysteresis (note 2) v ov(hys) 0.2 0.8 1.5 v logic supply voltage v dd 4.5 5.5 v logic supply current (note 3) i dd reset 0.7 v dd 1.0 4.0 ma reset 0.5 v 25 m a logic supply undervoltage lockout threshold (note 4) v dd(uvlo) 2.5 3.5 v power output draintosource on resistance (i out = 0.5 a, t j =25 c) r ds(on) w v pwr = 5.5 v 2.0 v pwr = 9.0 v 0.9 1.6 v pwr =13 v 0.7 1.4 draintosource on resistance (i out = 0.5 a, t j = 150 c) r ds(on) w v pwr = 5.5 v 3.0 v pwr = 9.0 v 1.2 2.0 v pwr =13 v 1.0 1.6 output self limiting current i out(lim) a outputs programmed on, v out = 0.6 v dd 1.0 2.0 3.0 output fault detect threshold (note 5) v outth(f) v output programmed off 2.5 3.0 3.5 output off open load detect current (note 6) i oco m a output programmed off, v out = 0.6 v dd 30 50 100 output clamp voltage v ok v 2.0 ma i out 200 ma 45 53 65 output leakage current (v dd 2.0 v) (note 7) i out(lkg) 25 0 25 m a over temperature shutdown (outputs off) (note 2) t lim 155 180 c over temperature shutdown hysteresis (note 2) t lim(hys) 10 20 c notes: 1. spi inputs and outputs operational; fault status reporting may not be fully operational within this voltage range. outputs wi ll remain operational somewhat below this v pwr range but r ds(on) will increase, causing power dissipation to increase. outputs will reestablish their instructed state following a v pwr interruption so long as v dd remains noninterrupted. 2. this parameter is guaranteed by design but is not production tested. 3. measured with the reset pin held at a logic high state; outputs can be off or on or in any combination thereof. 4. device incorporates a poweron reset function; for v dd less than the undervoltage lockout threshold voltage, all data registers are reset and all outputs are disabled. 5. output fault detect threshold with outputs programmed off. output fault detect thresholds are the same for output opens and s horts. 6. output off open load detect current is the current required to flow through the load for the purpose of detecting the existen ce of an open load condition when the specific output is commanded to be off. 7. output leakage current measured with the output off and at 16 v. MC33291L 5 motorola analog ic device data static electrical characteristics (continued) (characteristics noted under conditions of 4.5 v v dd 5.5 v, 9.0 v v pwr 16 v, 40 c t c 125 c, unless otherwise noted. typical values, where applicable, reflect the parameter's approximate average value with v bat = 13 v, t a = 25 c.) characteristic unit max typ min symbol digital interface input logic high voltage (note 1) v ih 0.7 1.0 v dd input logic low voltage (note 1) v il 0 0.2 v dd input logic voltage hysteresis (sclk, reset , and sfpd) (note 2) v i(hys) 50 100 500 mv si pullup current (si = 0 v) i si 0 10 20 m a csb pullup current (csb = 0 v) i csb 0 10 20 m a sclk pulldown current (sclk = 5.0 v) i sclk 0 10 20 m a reset pulldown current (reset = 5.0 v) i rstb 5.0 25 50 m a sfpd pulldown current (sfpd = 5.0 v) i sfpd 5.0 10 25 m a so high state output voltage (i oh = 1.0 ma) v soh v dd 0.4 v v dd 0.2 v v so low state output voltage (i ol = 1.6 ma) v sol 0.2 0.4 v so tristate leakage current (csb = 0.7 v dd , 0 v v so v dd ) i sot 10 0 10 m a input capacitance (0 v v dd 5.5 v) (note 3) c in 12 pf so tristate capacitance (0 v v dd 5.5 v) (note 4) c sot 20 pf notes: 1. upper and lower logic threshold voltage levels apply to si, csb, sclk, reset , and sfpd inputs. 2. hysteresis is characterized but not production tested. 3. input capacitance of si, csb, sclk, reset , and sfpd for 0 v v dd 5.5 v. this parameter is guaranteed by design but is not production tested. 4. tristate capacitance of so for 0 v v dd 5.5 v. this parameter is guaranteed by design but is not production tested. dynamic electrical characteristics (characteristics noted under conditions of 4.5 v v dd 5.5 v, 9.0 v v pwr 16 v, 40 c t c 125 c, unless otherwise noted. typical values, where applicable, reflect the parameter's approximate average value with v bat = 13 v, t a = 25 c.) characteristic symbol min typ max unit power output timing output rise time (v pwr = 13 v, r l = 26 w ) (note 1) t r 0.4 5.0 20 m s output fall time (v pwr = 13 v, r l = 26 w ) (note 1) t f 0.4 5.0 20 m s output turn on delay time (v pwr =13 v, r l = 26 w ) (note 2) t dly(on) 1.0 15 50 m s output turn off delay time (v pwr = 13 v, r l =26 w ) (note 3) t dly(off) 1.0 15 50 m s output short fault disable report delay (note 4) t dly(sf) m s sfpd = 0.2 v dd 70 150 250 output off fault report delay (note 5) t dly(off) m s sfpd = 0.2 v dd 70 150 250 notes: 1. output rise and fall time respectively measured across a 26 w resistive load at 10% to 90% and 90% to 10% voltage points. 2. output turn on delay time measured from 50% rising edge of csb to 90% of output off voltage (v pwr ) with r l = 26 w resistive load. 3. output turn off delay time measured from 50% rising edge of csb to 10% of output off voltage (v pwr ) with r l = 26 w resistive load. 4. propagation time of short fault disable report measured from 50% rising edge of csb to 10% output off voltage (v pwr ), v pwr = 6.0 v, and sfpd = 0.2 v dd . 5. output off fault report delay measured from 50% rising edge of csb to 10% rising edge of output off voltage (v pwr ). MC33291L 6 motorola analog ic device data dynamic electrical characteristics (continued) (characteristics noted under conditions of 4.5 v v dd 5.5 v, 9.0 v v pwr 16 v, 40 c t c 125 c, unless otherwise noted. typical values, where applicable, reflect the parameter's approximate average value with v bat = 13 v, t a = 25 c.) characteristic unit max typ min symbol digital interface timing required low state duration for reset (v il 0.2 v dd ) (note 1) t w(rstb) 50 167 ns falling edge of csb to rising edge of sclk (required setup time) t lead 50 167 ns falling edge of sclk to rising edge of csb (required setup time) t lag 50 167 ns si to falling edge of sclk (required setup time) t si(su) 25 83 ns falling edge of sclk to si (required hold time) t si(hold) 25 83 ns so rise time (c l = 200 pf) t r(so) 25 50 ns so fall time (c l = 200 pf) t f(so) 25 50 ns si, csb, sclk incoming signal rise time (note 2) t r(si) 50 ns si, csb, sclk incoming signal fall time (note 2) t f(si) 50 ns time from falling edge of csb to so low impedance (note 3) t so(en) 110 ns time from rising edge of csb to so high impedance (note 4) t so(dis) 110 ns time from rising edge of sclk to so data valid (note 5) t valid ns 0.2 v dd so 0.8 v dd , c l = 200 pf 65 105 notes: 1. reset low duration measured with outputs enabled and going to off or disabled condition. 2. rise and fall time of incoming si, csb, and sclk signals suggested for design consideration to prevent the occurrence of doub le pulsing. 3. time required for output status data to be available for use at so pin. 4. time required for output status data to be terminated at so pin. 5. time required to obtain valid data out from so following the rise of sclk (see figure 4). . ! . !$ ?>c 2a6 . . c <28 c a c 7 si c f+$#$ c +!9?<5 c +!bd .2<:5 c f+$# . . c <625 sclk . . c f*+, rstb csb ?>c 2a6 ?>c 2a6 .2<:5 . ! . !$ . ! . !$ . ! . !$ figure 2. input timing switching characteristics MC33291L 7 motorola analog ic device data c 7+' $?f c? :89 +' $ @ . . +$# MC33291L ->56a ,6bc note: c l represents the total capacitance of the test fixture and probe. c 7+! c a+! . . . . c e2<:5 c a+' . '$ . ' . '$ . ' c 5 . . . >b >b note: so (lowtohigh) is for an output with internal conditions such that the lowtohigh transition of csb causes the so output to switch from high to low. +' $ @ * $ ; w . (d<< -@ . . . + MC33291L ->56a ,6bc note: c l represents the total capacitance of the test fixture and probe. c a+! c 7+! . ,a: +c2c6 . ' c +'5:b . c +'5:b c +'6> c +'5:b c +'6> ,a: +c2c6 c? $?f . . . i >b i >b notes : 1. so is in a high or low tristate condition whenever csb is in a logic high state. 2. so is in either an active low or active high state, depending on whether the corresponding clocked output is faulted or not, when csb is in a logic low state. ,a: +c2c6 c? :89 :89 c? $?f figure 3. valid data delay time and valid time test circuit figure 4. valid data delay time and valid time waveforms figure 5. enable and disable time test circuit figure 6. enable and disable time waveforms . ,a: +c2c6 MC33291L 8 motorola analog ic device data 'dc@dc $ * $ w . (/* . . . + MC33291L ->56a ,6bc note: c l represents the total capacitance of the test fixture and probe. c 7+! c a+! . '$ . . '$ . . c 5 c 5 . i >b i >b ! 'dc<:= . ?> . '$ . ?77 . ('%(' (&& #' ('%(' $"' ! notes : 1. t pdly(off) is the output fault unlatch disable propagation delay time required to correctly report an output fault after csb rises. represents an output commanded on while having an existing output short (overcurrent) to supply. 2. sfpd pin 0.2 v c 5 MC33291L 10 motorola analog ic device data one main advantage of the MC33291L is the serial port which when coupled to an mcu, receives on/off commands from the mcu and in return transmits the drain status of the device's output switches. many devices can be adaisychainedo together to form a larger system (see figure 12). note in this example that only one dedicated mcu parallel port (aside from the required spi) is needed for chip select to control 32 possible loads. multiple MC33291L devices can also be controlled in a parallel input fashion using spi (see figure 13). this figure shows a possible 24 loads being controlled by only three dedicated parallel mcu ports used for chip select. +! + +$# 'dc@dcb +! + +$# 'dc@dcb +! + +$# MC33291L 'dc@dcb (2a2<<6< (?acb +$# %'+! %00 %:4a?4?>ca?<<6a +(! MC33291L MC33291L figure 13. parallel input spi control figure 14 shows a basic method of controlling multiple MC33291L devices using two mcus. a system can have only one master mcu at any given instant of time and one or more slave mcus. master control of the system must pass from one mcu to the other in an orderly manner. the master mcu supplies the system clock signal (top mcu designated the master); the lower mcu being the slave. it is possible to have a system with more than one master, but not at the same time. only when the master is not communicating can a slave assume the amastershipo and communicate. mcu master control is switched through the use of the slave select (ss) pin of the mcus. a master will become a slave when it detects a logic low state on its ss pin. some mcus have slave select override capability and one must consult the mcu manufacturer for the specific details. these basic examples make the MC33291L very attractive for applications where a large number of loads need be controlled efficiently. the popular synchronous serial peripheral interface (spi) protocol is incorporated, to this end, to communicate efficiently with the mcu. spi system attributes the spi system is flexible enough to communicate directly with numerous standard peripherals and mcus available from motorola and other semiconductor manufacturers. spi reduces the number of pins necessary for input/output (i/o) on the MC33291L. it also offers an easy means of expanding the i/o function using few mcu pins. the spi system of communication consists of the mcu transmitting, and in return, receiving one databit of information per system clock cycle. databits of information are simultaneously transmitted by one pin, microcontroller out serial in (mosi), and received by another pin, microcontroller in serial out (miso), of the mcu. some features of spi are: ? full duplex, threewire synchronous data transfer ? each microcontroller can be a master or a slave ? provides write collision flag protection ? provides end of message interrupt flag ? four i/os associated with spi (mosi, miso, sclk, ss) the only drawbacks to spi are that an mcu is required for efficient operational control and, in contrast to parallel input control, is slower at performing pulse width modulating (pwm) functions due to having to write an 8bit word. the dynamic range and accuracy of pwm functions is a direct result of the clock frequency used. :c MC33291L + +$# +' +! 'dc@dcb :c + +$# +' +! 'dc@dcb MC33291L :c MC33291L + +$# +' +! 'dc@dcb ++ :c %00 %:4a?4?>ca?<<6a +(! (master) %'+! %!+' (2a2<<6< (?acb +$# figure 14. multiple mcu spi control . ++ :c %00 %:4a?4?>ca?<<6a +(! (alternate master) %'+! %!+' (2a2<<6< (?acb +$# . MC33291L 11 motorola analog ic device data pin function description csb pin the system mcu selects the MC33291L to be communicated with through the use of the csb pin. whenever this pin is in a logic low state, data can be transferred from the mcu to the MC33291L via the si pin and from the MC33291L to the mcu via the so pin. clockedin data from the mcu is transferred from the MC33291L shift register and latched into the power outputs on the rising edge of the csb signal. on the falling edge of the csb signal, drain status information is transferred from the power outputs and loaded into the device's shift register. the csb pin also controls the output driver of the serial output pin (so). whenever the csb pin goes to a logic low state, the so pin output driver is enabled allowing information to be transferred from the MC33291L to the mcu. to avoid data corruption or the generation of spurious data, it is essential that the hightolow transition of the csb signal occur only when sclk is in a logic low state. sclk pin the system clock pin (sclk) clocks the internal shift registers of the MC33291L. the serial input pin (si) accepts data into the input shift register on the falling edge of the sclk signal while the serial output pin (so) shifts data information out of the so line driver on the rising edge of the sclk signal. false clocking of the shift register must be avoided to guarantee validity of data. it is essential that the sclk pin be in a logic low state whenever chip select bar pin (csb) makes any transition. for this reason, it is recommended though not necessary, that the sclk pin be kept in a low logic state as long as the device is not accessed (csb in logic high state). when csb is in a logic high state, signals at the sclk and si pins are ignored and so is tristated (high impedance). see the data transfer timing diagram of figure 15. si pin this pin is for the input of serial instruction data. si information is read in on the falling edge of sclk. a logic high state present on this pin when the sclk signal rises will program a specific output off, and in turn, turns off the specific output on the rising edge of the csb signal. conversely, a logic low state present on the si pin will program the output on, and in turn, turns on the specific output on the rising edge of the csb signal. to program the eight outputs of the MC33291L on or off, an eight bit serial stream of data is required to be synchronously entered into the si pin starting with output 7, followed by output 6, output 5, etc., to output 0. referring to figure 15; the d0 bit is the most significant bit (msb) corresponding to output 7. for each rise of the sclk signal, with csb held in a logic low state, a databit instruction (on or off) is synchronously loaded into the shift register per the databit si state. the shift register is full after eight bits of information have been entered. to preserve data integrity, care should be taken to not transition si as sclk transitions from a lowtohigh logic state. so pin the serial output (so) pin is the atristateableo output from the shift register. the so pin remains in a high impedance state until the csb pin goes to a logic low state. the so data reports the drain status, either high or low relative to the previous command word. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. when an output is off and not faulted, the corresponding so databit is a high state. when an output is on, and there is no fault, the corresponding databit on the so pin will be a low logic state. the si/so shifting of data follows a firstinfirstout (fifo) protocol with both input and output words transferring the msb first. referring to figure 15; the d0* bit is the msb corresponding to output 7 relative to the previous command word. the so pin is not affected by the status of the reset pin. reset pin the MC33291L reset pin is active low and is used to clear the spi shift register and in doing so sets all output switches off. with the device in a system with an mcu; upon initial system power up, the mcu holds the reset pin of the device in a logic low state insuring all outputs to be off until both the v dd and v pwr pin voltages are adequate for predictable operation. after the MC33291L is reset, the mcu is ready to assert system control with all output switches initially off. if the v pwr pin of the MC33291L experiences a low voltage, following normal operation, the mcu should pull the reset pin low so as to shutdown the outputs and clear the input data register. the reset pin is active low and has an internal pulldown incorporated to insure operational predictability should the external pulldown of the mcu open circuit. the internal pulldown is only 25 m a to afford safe and easy interfacing to the mcu. the reset pin of the MC33291L should be pulled to a logic low state for a duration of at least 250 ns to insure reliable reset. sfpd pin the short fault protect disable (sfpd) pin is used to prevent the outputs from latchingoff because of an overcurrent condition. this feature allows control of incandescent loads where inrush currents exceed the device's analog current limits. essentially the sfpd pin determines whether the MC33291L output(s) will instantly shutdown upon sensing an output short or remain on in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. if the sfpd pin is tied to v dd = 5.0 v the MC33291L output(s) will remain on in a current limited mode of operation upon encountering a load short to supply or over current condition. if the sfpd pin is grounded, a short circuit will immediately shut down only the output affected. other outputs not having a fault condition will operate normally. the short circuit operation is addressed in more detail later. MC33291L 12 motorola analog ic device data sclk si so csb output 7 output 0 ' ' ' ' ' ' ' ' '<5 2c2 '<5 2c2 &6f 2c2 ' &6f 2c2 ' notes: 1. reset pin is in a logic highstate during the above operation. 2. d0, d1, d2, ..., and d15 relate to the ordered entry of program data into the mc33291 with d0/d8 bits (msb) corresponding to output 7 and d7/d15 corresponding to output 0. 3. d0*, d1*, d2*, ..., and d7* relate to the ordered data out of the mc33291 with d0* bit (msb) corresponding to output 7. 4. od* corresponds to old databits. 5. for brevity, only do7 and do0 are shown which respectively correspond to output 7 and output 0. data transfer timing (general) csb hightolow csb lowtohigh so si so pin is enabled. output status information transferred to output shift register. data from the shift register is transferred to the output power switches. will change state on the rising edge of the sclk pin signal. will accept data on the falling edge of the sclk pin signal. figure 15. data transfer timing figure 15. MC33291L 13 motorola analog ic device data power consumption the MC33291Ldw has extremely low power consumption in both the operating and standby modes. in the standby or asleepo mode, with v dd 2.0 v, the current consumed by the v pwr pin is less than 25 m a. in the operating mode, the current drawn by the v dd pin is less than 4.0 ma (1.0 ma typical) while the current drawn at the v pwr pin is 2.0 ma maximum (1.0 ma typical). during normal operation, turning outputs on increases i pwr by only 20 m a per output. each output experiencing a asoft shorto (overcurrent conditions just under the current limit), adds 0.5 ma to the i pwr current. paralleling of outputs using mosfets as output switches allows the connection of any combination of outputs together. r ds(on) of mosfets have an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation (bipolar outputs could not be paralleled in this fashion as thermal runaway would likely occur). the device can even be operated with all outputs tied together. this mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. performance of parallel operation results in a corresponding decrease in r ds(on) while the output off open load detect currents and the output current limits increase correspondingly (by a factor of eight if all outputs are paralleled). less than 125 m w r ds(on) at 25 c with current limiting of 8 to 24 a will result if all outputs are paralleled together. there will be no change in the overvoltage detect or the off output threshold voltage range. the advantage of paralleling outputs within the same MC33291L affords the existence of minimal r ds(on) and output clamp voltage variation between outputs. typically, the variation of r ds(on) between outputs of the same device is less than 0.5%. the variation in clamp voltages (which could affect dynamic current sharing) is less than 5%. paralleling outputs from two or more different devices is possible but not recommended. this is because there is no guarantee that the r ds(on) and clamp voltage of the two devices will match. system level thermal design analysis and verification should be conducted whenever paralleling outputs; particularly where different devices are involved. fault logic operation general the mcu can perform a parity check of the fault logic operation by comparing the command 8bit word to the status 8bit word. assume that after system reset, the mcu first sends an 8bit command word (command word 1) to the MC33291L. each output that is to be turned on will have its corresponding databit low. refer to the data transfer timing diagram of figure 15. as command word 1 is being written into the shift register of the MC33291L, a status word is being simultaneously written out and received by the mcu. however, the word being received by the mcu is the status of the previous command word written to the MC33291L (status word 0). if the same command word of the mcu is written a second time (command word 2 = command word 1), the word received by the mcu, status word 2, is the status of command word 1. the timing diagram shown in figure 15 depicts this operation. status word 2 is then compared with command word 1. the mcu will exclusive or status word 2 with command word 1 to determine if the two status words are identical. if the two status words are identical, no faults exist. if the two status words differ, there exists a fault and further status word analysis is necessary to determine the cause. the timing between the two write words must be greater than 100 m s so as to allow adequate time to sense and report the proper drain status. the system databus integrity may be tested by writing two like words to the MC33291L within a few microseconds of each other. initial system setup timing the mcu can monitor two kinds of faults: (1) communication errors on the data bus and (2) actual faults of the output loads. after initial system start up or reset, the mcu will write one word to the MC33291L. if the word is repeated within a few microseconds (say 5) of the first word, the word received by the mcu, at the end of the repeated word, serves as a confirmation of data bus integrity (1). at startup, the MC33291L will take 70 to 250 m s before a repeat of the first word can give the actual status of the outputs. therefore, the first word should be repeated at least 250 m s later to verify the status of the outputs. the so pin of the MC33291L will indicate any one of four faults. the four possible faults are over temperature, output off open fault, short fault (overcurrent), and v pwr overvoltage fault. all of these faults, with the exception of the overvoltage fault, are output specific. over temperature detect, output off open detect, and output short detect are dedicated to each output separately such that the outputs are independent in operation. a v pwr overvoltage detect is of a aglobalo nature causing all outputs to be turned off. over temperature fault over temperature detect and shutdown circuits are specifically incorporated for each individual output. the shutdown that follows an over temperature condition is independent of the system clock or any other logic signal. each independent output shuts down at 155 to 185 c. when an output shuts down due to an over temperature fault, no other outputs are affected. the mcu recognizes the fault since the output was commanded to be on and the status word indicates that it is off. a maximum hysteresis of 20 c ensures an adequate time delay between output turn off and recovery. this avoids a very rapid turn on and turn off of the device around the over temperature threshold. when the temperature falls below the recovery level for the over temperature fault, the device will turn on only if the command word during the next write cycle indicates the output should be turned on. overvoltage fault an overvoltage condition on the v pwr pin will cause the MC33291L to shutdown all outputs until the overvoltage condition is removed and the device is reprogrammed by the spi. the overvoltage threshold on the v pwr pin is specified as 28 to 36 v with 1.0 v typical hysteresis. following the overvoltage condition, the next write cycle sends the so pin the hexadecimal word $ff (all ones) indicating all outputs are turned off. in this way, potentially MC33291L 14 motorola analog ic device data dangerous timing problems are avoided and the mcu reset routine ensures an orderly startup of the loads. the MC33291L does not detect an overvoltage on the v dd pin. other external circuitry, such as the motorola mc33161 universal voltage monitor, is necessary to accomplish this function. output off open load fault an output off open load fault is the detection and reporting of an aopeno load when the corresponding output is disabled (input bit programmed to a logic high state). to understand the operation of the open load fault detect circuit, see figure 16. the output off open load fault is detected by comparing the drain voltage of the specific mosfet output to an internally generated reference. each output has one dedicated comparator for this purpose. MC33291L * $ . (/* %'+ , ' $?f 2d . 'dc@dc figure 16. output off open load detect an output off open load fault is indicated when the output voltage is less than the output threshold voltage (v thres ) of 2.5 to 3.5 v. since the MC33291L outputs function as switches, during normal operation, each mosfet output should either be completely turned on or off. by design the threshold voltage was selected to be between the on and off voltage of the mosfet. during normal operation, the on state v ds voltage of the mosfet is less than the minimum threshold voltage and the off state v ds voltage is greater than the maximum threshold voltage. this design approach affords using the same threshold comparator for output open load detect in the off state and short circuit (or overcurrent) detect in the on state. see figure 17 for an understanding of the short circuit detect circuit. an off state output voltage of less than 2.5 v will be detected as an output off open load fault (output open) while voltages greater than 3.5 v will not be detected as a fault. the MC33291L has an internal pulldown current source of 50 m a, as shown in figure 16, between the mosfet drain and ground. this prevents the output from floating up to v pwr if there is an open load or internal wirebond failure. the internal comparator compares the drain voltage with a reference voltage, v thres . if the output voltage is less than this reference voltage, the MC33291L will declare the condition to be an open load fault. during output switching, especially with capacitive loads, a false output off open load fault may be triggered. to prevent this false fault from being reported an internal fault filter of 70 to 250 m s is incorporated. the duration for which a false fault may be reported is a function of the load impedance (r l , c l , l l ), r ds(on) , and c out of the mosfet as well as the supply voltage, v pwr . the rising edge of csb triggers a builtin fault delay timer which must time out (70 to 250 m s) before the fault comparator is enabled to detect a faulted threshold. the circuit automatically returns to normal operation once the condition causing the open load fault is removed. shorted load fault a shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. there are three safety circuits progressively in operation during load short conditions which afford system protection; 1) the device's output current is monitored in an analog fashion using a sensefet ? approach and current limited, 2) the device's output current is sensed by monitoring the mosfet drain voltage, and 3) the device's output thermal limit is sensed and when attained causes only the specific faulted output to be latched off, allowing all remaining outputs to operate normally. all three protection mechanisms are incorporated in each output affording robust independent output operation. the analog current limit circuit is always active and monitors the output drain current. an overcurrent condition causes the gate control circuitry to reduce the gatetosource voltage imposed on the output mosfet which reestablishes the load current in compliance with current limit (1.0 to 3.0 a) range. the time required for the current limit circuitry to act is less than 20 m s. therefore, currents h igher than 1.0 to 3.0 a will never be seen for more than 20 m s (a typical duration is 10 m s). if the current of an output attempts to exceed the predetermined limit of 1.0 to 3.0 a (2.0 a nominal), the v ds voltage will exceed the v thres voltage and the overcurrent comparator will be tripped as shown in figure 17. figure 17. short circuit detect and analog current limiting circuit MC33291L * $ . (/* %'+ , '& :89 2d . 'dc@dc >2MC33291L will shut down immediately or continue to operate in an analog current limited mode until either the short circuit (overcurrent) condition is removed or thermal shutdown is reached. grounding the sfpd pin will enable the short fault protection shutdown circuitry. consider a load short (output short to supply) occurring on an output before, during, and MC33291L 15 motorola analog ic device data after output turn on. when the csb signal rises to the high logic state, the corresponding output is turned on and a delay timer activated. the duration of the delay timer is 70 to 250 m s. if the short circuit takes place before the output is turned on, the delay experienced is the entire 70 m s to 250 m s followed by shutdown. if the short occurs during the delay time, the shutdown still occurs after the delay time has elapsed. if the short circuit occurs after the delay time, shutdown is immediate (within 20 m s after sensing). the purpose of the delay timer is to prevent false faults from being reported when switching capacitive loads. if the sfpd pin is at 5.0 v (or v dd) , an output will not be disabled when an overcurrent is detected. the specific output will, within 5.0 to 10 m s of encountering the short circuit, go into an analog current limited mode. this feature is especially useful when switching incandescent lamp loads, where high inrush curr ents experienced during startup last for 10 to 20 milliseconds. each output of the MC33291L has its own overcurrent shutdown circuitry. over temperature faults and the overvoltage faults are not affected by the sfpd pin's state. both load current sensing and output voltage sensing are incorporated for short fault detection with actual detection occurring slightly after the onset of current limit. the current limit circuitry incorporates a asensefet ? o approach to measure the total drain current. this calls for the current through a small number of cells in the power mosfet to be measured and the result multiplied by a constant to give the total current. wherein output shutdown circuitry measures the draintosource voltage and shuts down the output if its threshold (v thres ) is exceeded. short fault detection is accomplished by sensing the output voltage and comparing it to v thres . the lowest v thres requires a voltage of 2.5 v to be sensed. for an enabled output, with v dd = 5.0 0.5 v, an output voltage in excess of 3.5 v will be detected as a ashorto (overcurrent condition) while voltages less than 2.5 v will not be detected as ashorts.o over current recovery if the sfpd pin is in a high logic state, the circuit returns to normal operation automatically after the short circuit is removed (unless thermal shutdown has occurred). if the sfpd pin is grounded and overcurrent shutdown occurs, removal of the short circuit will result in the output remaining off until the next write cycle. if the short circuit is not removed, the output will turn on for the delay time (70 to 250 m s) and then turn off for every write cycle commanding a turn on. sfpd pin voltage selection since the voltage condition of the sfpd pin controls the activation of the short fault protection (i.e. shutdown) mode equally for all eight outputs, the load having the longest duration of inrush current determines what voltage (state) the sfpd pin should be at. usually if at least one load is, say an incandescent lamp, the inrush current on that input will be milliseconds in duration. therefore, setting sfpd at 5.0 v will prevent shutdown of the output due to the inrush current. the system relies only on the over temperature shutdown to protect the outputs and the loads. the MC33291L was designed to switch ge194 incandescent lamps (or equivalents) with the sfpd pin in a grounded state. considerably larger lamps can be switched with the sfpd pin held in a high logic state. sometimes both a delay period greater than 70 to 250 m s (current limiting of the output) followed by an immediate over current shutdown is necessary. this can be accomplished by programming the sfpd pin to 5.0 v for the extended delay period to afford the outputs to remain on in a current limited mode and then grounding it to accomplish the immediate shutdown after some period of time. additional external circuitry is required to implement this type of function. an mcu parallel output port can be devoted to controlling the sfpd voltage during and after the delay period, is often a much better method. in either case, care should be taken to execute the sfpd startup routine every time startup or reset occurs. undervoltage shutdown an undervoltage v dd condition will result in the global shutdown of all outputs. the undervoltage threshold is between 2.5 v and 3.5 v. when v dd goes below the threshold, all outputs are turned off and the so data register is reset to indicate the same. an undervoltage condition at the v pwr pin will not cause output shutdown and reset. when v pwr is between 5.5 v and 9.0 v, the outputs will operate per the command word. however, the status as reported by the serial output (so) pin may not be accurate below 9.0 v v pwr . proper operation at v pwr voltages below 5.5 v can not be guaranteed. deciphering fault type the MC33291L so pin can be used to understand what kind of system fault has occurred. with eight outputs having open load, over current, over temperature, and over voltage faults; a total of 25 dif ferent faults are possible. the so status word received by the mcu will be compared with the word sent to the MC33291L during the previous write cycle. for a specific output, if the so bit compares with the corresponding si bit of the previous word; the output is operating normal with no fault. only when the so bit and previous word si bit differ is there a fault indicated. if the two words are not the same, then the mcu should be programmed to determine which output or outputs are faulted. if for a specific output, the initial si command bit were logic high, the output would be programmed to be aoffo; if upon the next command word being entered, a logic low came back on so, for that specific output's corresponding bit, an aoutputoff openloado fault would be indicated. the resulting so bit, for that specific output, would be different from that entered during the previous word for that si bit, indicating the fault. the eight outputoff openload faults are therefore most easily detected. if for a specific output, the initial si command bit were a logic low, calling for the output to be programmed aono; upon the next word command being entered, the corresponding bit came back with a logic high on so, an output over current fault would be indicated. an over current fault is always reported by the so output and is independent of the logic state existing on the sfpd pin. it should be pointed out that when the sfpd pin is in a logic high state, an over current condition will be reported on the so pin but output current limiting will be in effect and the output will be permitted to operate so long as the over current condition does not drive output into an over temperature fault. an over temperature fault will shutdown the specific output effected for the duration of the over temperature condition. MC33291L 16 motorola analog ic device data over current and over temperature faults are often related. turning the effected output switches off and waiting for some time to allow the output to cool down should make these types of faults go away. asofto over current faults can sometimes be determined over hard short faults and over temperature faults by observing the time required for the device to recover. in general though, over current and over temperature faults can not be differentiated in normal application usage. one advantage of the synchronous serial output is that multiple faults can be detected with only one pin (so) being used for fault status reporting. if v pwr experiences an overvoltage condition, all outputs will immediately be turned off and remain latched off. a new command word is required to turn the outputs back on following an overvoltage condition. 1st cmd word 2nd cmd word status si so si so (note 1) (note 2) (note 3) h x h h ok/normal/output aoffo l x l l ok/normal/output aono h x h l fault/outputoff open l x l h fault/output over current or thermal shutdown or overvoltage shutdown notes: 1. during the first command word, the so output status word is to be ignored (don't care). 2. during the second command word, the so output status word is independent of the second command word si input data; so results are only valid for the si data entered during the first (previous) command word. 3. output faults due to over current, over temperature, or over voltage can be determined but require additional interrigation in order to differentiate the actual cause. output voltage clamping each output of the MC33291L incorporates an internal voltage clamp to provide fast turnoff and transient protection of the output. each clamp independently limits the drain to source voltage to 53 v at drain currents of 0.5 a and keeps the output transistors from avalanching by causing the transient energy to be dissipated in the linear mode (see figure 18). the total energy clamped (e j ) can be calculated by multiplying the current area under the current curve (i a ) times the clamp voltage (v cl ) times the duration the clamp is active (t). characterization of the output clamps, using a single pulse nonrepetitive method at 0.5 a, indicate the maximum energy to be 50 mj at 150 c junction temperature per output. <2=@ >6a8h " ! g . $ g c a2:> .? a2:> c? +?da46 <2=@ .? MC33291L 17 motorola analog ic device data b 74.3 73.1 70.1 70.1 70.1 69.8 70.8 72.5 72.7 74.8 70.3 70.1 69.8 69.5 69.9 71.0 68.7 69.1 73.0 70.9 69.2 68.4 67.8 68.3 68.4 68.3 70.7 72.1 70.4 69.0 67.8 68.1 68.6 68.1 69.6 70.8 72.9 71.2 68.7 68.6 68.2 68.2 68.4 69.2 71.1 73.1 68.8 68.6 69.3 69.0 68.1 68.5 69.2 69.5 73.3 71.2 70.0 68.6 67.8 67.9 68.4 68.4 70.7 71.8 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 t a tj 0 tj 1 tj 2 tj 3 tj 4 tj 5 tj 6 tj 7 where b 7 i 1 q i 0.45 13.0389 figure 19. steady state thermal matrix equation latchup immunity device latchup caused by substrate injection has been characterized. latchup immunity has both a dc and a transient immunity component. dc latchup immunity results indicate the device to be capable of withstanding in excess of four amps of reverse current out of any of the output transistors while the control logic continues to function normally. the logic control current (i dd ) was found to increase by only 0.6 ma with four amps of current being pulled out of an output. additionally, the i pwr current was found to increase by only 0.15 ma under the same condition. these increases are a result of minority carriers being injected into substrate and subsequently collected. the following procedure has been developed to test for transient latchup immunity and has been applied to this automotive circuit design. results of transient testing indicate the device to operate properly at output currents greater than 1.5 a. the procedure tests for the device's immunity to intermittent loadtobattery current connection with the device controlling an inductive load. using the appropriately termed athe file test,o the battery is connected to a shop file while the lead to the inductive load is dragged across the files surface causing intermittent load opens producing lots of arcs, sparks, and smoke, plus severe transients (see figure 20). it is during these severe transients that latchup most likely could occur. the battery voltage used for this test was 18 v and the inductive load was 2.0 mh. these values were found to produce severe transient stresses of the device outputs. all outputs must maintain operation and input control during transient generation to pass athe file test.o the device's input control currents were found to remain stable and were not affected by dc or transient latchup immunity testing in most all cases. figure 20. transient latchup immunity file test 2cc6ah m ! <:=:c 'dc@dc * + '@6> $?25 6c64c +9?ac :a4d:c 6c64c 'e6a ,6=@6a2cda6 6c64c +' +! +$# + *6b6c + ( . 2c6 ?>ca?< . 'dc@dcb ic?i a?d>5b . (/* MC33291L 18 motorola analog ic device data applications information siop communication two common communication protocols used in motorola's microcontrollers are the serial peripheral interface (spi) and synchronous input output port (siop). siop is a subset of the more flexible spi and the simpler of the two protocols. siop is used on many of the mc68hc05 family of microcontrollers. restrictions of the siop protocol include: 1) the sclk frequency is fixed at onefourth the internal clock rate and 2) the polarity of the sclk signal is fixed. by way of example, the mc68hc05p9 utilizes siop protocol and is not directly compatible with the serial input requirements of the MC33291L. specifically, the MC33291L accepts data on the falling edge of sclk whereas its rising edge triggers data transfer in the siop protocol. sclk is high during siop transmissions, which is the opposite of what the MC33291L requires. though designed specifically for spi communication protocol, the MC33291L can easily be adapted to communicate with siop protocol through the use of software. the amount of code required to implement spi in software is relatively small, so the only major drawback is a slower transfer of data. the software routine shown in table 1 completes a transfer in about 100 m s. cost the bottom line relates to cost. the MC33291L is a very cost effective octal output serial switch for applications typically encountered in the automotive and industrial market segments. to accomplish only the most basic serial switch function the MC33291L offers, using a discrete semiconductor approach, would require the use of at least eight logic level power mosfets for the outputs and two shift registers for the i/o plus other miscellaneous aglueo components. additional circuitry would have to be incorporated to accomplish the protection features offered by the MC33291L. other noteworthy advantages the MC33291L offers are conservation of power and board space, requirement of fewer application components, and enhanced application reliability. the MC33291L is available at a fraction of the cost required for discrete component implementation and represents true value. the bottom line is; the MC33291L represents a cost effective device having advanced performance and features and worthy of consideration. hope you find the device satisfactory for your application. table 1. program to exercise the MC33291L using spi (having only siop) protocol set labels for output registers porta equ $0000 ;spi port ;do (data out), sclk, cs, r eset , x, fltout, di (data in) portb equ $0001 ;normally the siop port. siop will be disabled. portc equ $0002 ;ad converter port portd equ $0003 ;timer capture port ddra equ $0004 ;data direction register for spi port ddrb equ $0005 ;data direction register for sclk, sdi, sdo, 1 1111 ddrc equ $0006 ;data direction register for ad converter port ddrd equ $0007 ;data direction register for portd, timer capture dtout equ $0080 ;register for the spi output data. this register will be used for a serialtoparallel transformation datain equ $0081 ;input register for spi. also used for a serialtoparallel transformation value equ $0082 ;register to store the spi output word for fault testing data1 equ $0083 ;miscellaneous data register scr equ $000a ;label for siop control register, 0 spe 0 mstr 0 0 0 0 ssr equ $000b ;label for siop status register, spif dcol 0 0 0 0 0 0, read only register sdr equ $000c ;label for siop data register org $0100 ;program starts at first byte of user rom init rsp ;reset stack pointer to $ff MC33291L 19 motorola analog ic device data table 1. program to exercise the MC33291L using spi (having only siop) protocol (continued) initialize the data registers and their data direction bit registers lda #$fe ;configure port a as the spi port sta ddra ;all but bit 0 will be outputs lda #$ff sta ddrb ;configure register b as an output. siop is not used for the MC33291L but is available for another peripheral. sta ddrc ;configure register c as an output sta ddrd ;configure register d as an output lda #%00010000 ;initialize the siop control register sta scr ;disable siop by clearing bit 6 select the desired outputs top lda sta #$55 value ;select outputs of MC33291L to be turned on. this instruction is left inside the loop to include changes while running the program. a set bit will cause the associated MC33291L output to be off. the value register is uncorrupted by the serialtoparallel conversion. bset 4,porta ;reset the MC33291L bclr 4,porta ;also establishes a + or trigger source bset 4,porta ;the MC33291L is reset with a logic low bclr 5,porta ;enable MC33291L by pulling csb (chip select bar) low. within the MC33291L the fault status is transferred to the MC33291L serial register at a falling edge of csb lda value ;select outputs to be turned on sta dtout ;save output word (value) to check for fault spi transfer loop ldx #$07 ;set the number of read/shift cycles loop asl datain ;shift a zero into lsb of datain and asl other bits asl dtout ;test value currently in msb of dtout bcs doone ; bclr 7,porta ;msb was zero, so clear data out bit jmp goon doone bset 7,porta ;msb was one, so set the data out bit goon bset 6,porta ;set the sclk. serial output pin of the MC33291L changes state on the rising edge of the sclk. read the next bit coming from the MC33291L. brclr 0,porta, wzzer0 ;read the bit and branch if zero. lsb of datain is already cleared due to the asl above. bset 0,datain ;bit was one, set the next bit in datain wzzer0 bclr 6,porta ;clear sclk. falling edge causes the MC33291L to read the next bit from the mcu. decx bpl loop ;continue to loop eight times until the spi transfer is complete bset 5,porta ;transfer control signal to output transistors MC33291L 20 motorola analog ic device data table 1. program to exercise the MC33291L using spi (having only siop) protocol (continued) establish a brief delay lda #16 pause deca ;3 clock cycles bne pause ;3 clock cycles bclr 5,porta ;transfer output status to serial register jsr fltchk ;jump to fault check subroutine jsr dly ;delay 1/t msec bset 5,porta ;deselect the MC33291L bra top ;return to top of loop subroutine to check for faults fltchk bclr 1,porta ;clr the fault pin lda datain cmp value ;check for faults beq noflt ;if there is no fault, continue bset 1,porta ;activate fault led noflt rts delay subroutine dly sta data1 ;save accumulator in ram lda #$04 ;do outer loop 4 times, roughly 4 ms. outlp clrx ;x used as inner loop count innrlp decx ;0ff, fffe, 10 256 loops bne innrlp ;6cyc* 256* 1 m s/cyc = 1.53 ms deca ;43, 32, 21, 10 bne outlp ;1545cyc* 4*1 m s/cyc = 6.18 ms lda data1 ;recover accumulator value rts ;return from subroutine org $1ff fdb init MC33291L 21 motorola analog ic device data dw suffix plastic package case 751e04 sop (16+4+4)l issue e outline dimensions &', + !% &+!'&!& & ,'$ *&!& ( * &+! 1 % '&,*'$$!& !% &+!'& %!$$!% , * !% &+!'&+ & ' &', !&$- %'$ (*',*-+!'& %0!%-% %'$ (*',*-+!'& ( * +! !% &+!'& ' + &', !&$- %* (*',*-+!'& $$'/$ %* (*',*-+!'& + $$ ,',$ !& 0 ++ ' !% &+!'& , %0!%-% %, *!$ '& !,!'& a b p 12x d 24x % % + % + , t g 22x k c r x 45 m f j + + MC33291L 22 motorola analog ic device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operatin g parameters, including at ypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a s ituation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed : motorola literature distribution; p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 japan : motorola japan ltd.; sps, technical information center, 3201, minamiaz abu. minatoku, tokyo 1068573 japan. 8 1334403569 asia/pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong ko ng. 85226668334 technical information center: 18005216274 home page : http://www.motorola.com/semiconductors/ MC33291L/d ? |
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